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YMF753
AC'97 Revision2.2 Audio CODEC with Digital Audio I/F
OVERVIEW
YMF753 is an AC'97 Audio CODEC LSI, which is fully compliant with the industry standard "Audio CODEC '97" component specification (Revision 2.2). Different from former AC'97, YMF753 supports new features like SPDIF OUT and Zoomed Video Port. Without using a digital controller, these new features can be enhanced in the AC'97 sound system that has an ICH controller built-in chipset. Low power consumption is supported not only in the normal mode but can be controlled in the power-down mode.
FEATURES
* AC'97 Revision 2.2 Compliant * Exceeds PC99 / PC2001 Analog Performance Requirement (Mobile PC Audio Performance Compliant when analog low power supply is used.) * Analog Inputs : - 4 Stereo Inputs: LINE, CD, VIDEO, AUX - 2 Monaural Inputs: Speakerphone and PC BEEP Inputs - 2 Independent Microphone Inputs * PC BEEP can directly output to Line Out * Internal +20dB amplifier circuitry for microphone * Analog Outputs : Stereo LINE Output, True LINE Level and Monaural Output * Supports Zoomed Video Port * Supports Consumer IEC958 Output Port (SPDIF OUT) * SPDIF Output for AC'97 Revision 1.0 Compliant * Different audio data from AC-Link can be output to SPDIF and Line Out * Supports 3D Enhancement (Wide Stereo), and Bass / Treble control * Multiple CODEC Capability * Programmable Power Down Mode * Supports EAPD (External Amplifier Power Down) * Power Supplies : Analog 4.3V to 5.0V, Digital 3.3V or 5.0V * 48-Pin SQFP Package (YMF753-S)
YAMAHA CORPORATION
YMF753 CATALOG 1998 Decembe 3, CATALOG No.:LSI-4MF753A2 March 6, 2001
SDATA_OUT
SDATA_IN XTL_IN XTL_OUT
YMF753
PC_BEEP DVdd1 DVss2 DVss1 SYNC 9 8 7 6 5 4 3 2 1 BIT_CLK RESET# DVdd2 11 ZV_BCK / DIT EAPD (DIT) EXT24M / ID1# Reserved / ID0# ZV_SIN / Reserved ZV_LR / DIT 43 42 41 40 39 38 37 25 26 27 28 29 30 31 32 33 34 35 36 AVss2 LNLVL_OUT_R MSEL LNLVL_OUT_L AVdd2 MONO_OUT 10 12
PHONE 48 47 46 45 44 AUX_L AUX_R 16 17 18 19 20 21 22 23 24 15 14
PIN CONFIGURATION
13
VIDEO_L
VIDEO_R CD_L
CD_GND CD_R MIC1 MIC2
48-Pin SQFP Top View
2
Vref CAP1 CAP2 CAP3 CAP4 CAP5 CAP6 AVss1 AVdd1 Vrefout LINE_OUT_L
LINE_IN_L
LINE_IN_R
LINE_OUT_R
March 6, 2001
YMF753
PIN DESCRIPTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Name DVdd1 XTL_IN XTL_OUT DVss1 SDATA_OUT BIT_CLK DVss2 SDATA_IN DVdd2 SYNC RESET# PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R AVdd1 AVss1 Vref I/O I O I I/O O I I AI AI AI AI AI AI AI AI AI AI AI AI AI AO Function Digital power supply (Typ. +3.3V / +5.0V) Connect to the digital ground with 0.1mF and 47mF capacitors. Connect this pin to DVdd2. 24.576MHz Clock Input 24.576MHz Clock Output Digital ground. Connect this pin to DVss2. AC'97 Serial Input Stream AC'97 Bit Clock As an output pin at the primary codec where CODEC ID=00. As an input pin at the secondary codec where CODEC ID=01,10,11. Digital ground. Connect this pin to DVss1. AC'97 Serial Output Stream Digital power supply (Typ. +3.3V / +5.0V) Connect to the digital ground with 0.1mF and 47mF capacitors. Connect this pin to DVdd1. SYNC Input (Fixed at 48kHz) Hardware Reset PC Speaker Beep Telephony Input AUX Input Left Channel AUX Input Right Channel Video Audio Input Left Channel Video Audio Input Right Channel CD Audio Input Left Channel CD Audio Analog Ground Connect this pin to CD Ground or Analog Ground. CD Audio Input Right Channel Microphone Input 1 Microphone Input 2 Line Input Left Channel Line Input Right Channel Analog Power Supply (Typ. +4.3V to +5.0V) Connect to the analog ground with 0.1mF and 47mF capacitors. Connect this pin to AVdd2. Analog ground. Connect this pin to AVss2. Analog Reference Voltage Connect to the analog ground with 0.1mF and 22mF capacitors. Analog Reference Voltage Output 28 Vrefout AO Connect to the analog ground with 0.1mF and 22mF capacitors when it is used to the external circuit.
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YMF753
No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 47 Name CAP1 CAP2 CAP3 CAP4 CAP5 CAP6 LINE_OUT_L LINE_OUT_R MONO_OUT AVdd2 LNLVL_OUT_L MSEL LNLVL_OUT_R AVss2 EAPD (DIT) I/O A A A A A A AO AO AO AO I AO O Function Connect to the analog ground with a 2200pF capacitor. Connect to the analog ground with a 0.015mF capacitor. Connect to the analog ground with a 0.01mF capacitor. Connect to the analog ground with a 2200pF capacitor. Connect to the analog ground with a 0.015mF capacitor. Connect to the analog ground with a 0.01mF capacitor. Line Output Left Channel Line Output Right Channel Monaural Output Analog power supply (Typ. +4.3V to +5.0V) Connect to the analog ground with 0.1mF and 47mF capacitors. Connect this pin to AVdd1. True LINE Level Output Left Channel Mode Select, which changes the pin function of No.43 - 46, 48. True LINE Level Output Right Channel Analog ground. Connect to AVss1. The function is selected at 62h TX-7 bit. TX-7="0", External Amplifier Power Down TX-7="1", Digital Audio Interface Output (48kHz)
1. MSEL= "High" (Connect to analog power supply.)
No. 43 44 45 46 48 Name ZV_LR ZV_SIN Reserved EXT24M ZV_BCK I/O IIO IFunction Zoomed Video Port L/R clock Zoomed Video Port serial data Do not connect externally. 24.576MHz clock output Zoomed Video Port bit clock
2. MSEL= "Low" (Connect to analog ground.)
No. 43 44 45 46 48 Name DIT Reserved CODEC ID0# CODEC ID1# DIT I/O O I+ I+ O Function Digital Audio Interface Output (48kHz) Do not connect externally. CODEC ID CODEC ID Digital Audio Interface Output (48kHz)
Note) AI: Analog Input Pin, AO: Analog Output Pin, I+: Input Pin with a Pull-up resistor, I-: Input Pin with a Pull-down resistor
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YMF753
BLOCK DIAGRAM
DVdd(2)
Power down Control
VREF
0dB/ +20dB
Record R 16step Record L 16step
AVdd(2)
MS
DVss(2)
AVss(2)
Vrefout
CAP6
CAP5
CAP4
CAP3
CAP2
CAP1
Vref
MIC1 MIC2 LINE_IN_R LINE_IN_L CD_R CD_GND CD_L VIDEO_R VIDEO_L AUX_R AUX_L PHONE
A/D A/D
RESET# SYNC BIT_CLK SDATA_OUT SDATA_IN Volume Control
CD Right
MUX
BUF
CD Left
AC'97 digital I/F
SPSA ID0/1#
LPBK PCM L 32step PCM R 32step ZV L 32step ZV R 32step
D/A
UDS
TX-7
DIT
PHONE 32step
EAPD (DIT) Reserved / ID0# MUX EXT24M / ID1# ZV_LR / DIT ZV_SIN / Reserved ZV_BCK / DIT MSEL Timing Generator
ID0# ID1# DIT ZV_LR ZV_SIN ZV_BCK EXT24M
D/A
AUX 32step VIDEO 32step CD 32step LINE 32step MIC 32step PC Beep 16step
ZV Port
Monaural 32step MIX
MONO_OUT PC_BEEP
RESET# Left
XTL_IN
3D tone
Right POP
Master L 32step Master R 32step
LINE_OUT_L LINE_OUT_R LNLVL_OUT_L LNLVL_OUT_R
XTL_OUT
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YMF753
MIXER REGISTERS
NAME 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 26h Reset Master vol. LNLVL vol. D15 D14 D13 D12 D11 D10 "0" Mute "0" ID0 * 3D "0" "0" "0" "0" D9 "0" D8 "0" D7 "0" BA2-0 GL4-0 GL4-0 GL4-0 GL4-0 GL4-0 SL2-0 GL3-0 WD3-1 MIX MS LPBK D6 "1" 20dB
D5 "0"
D4 "0"
D3 "0"
D2 "0"
D1 "0"
D0 Default "0" 0040h 8000h
ML5-0 -
MR5-0 -
0000h 8000h
Master vol. Mono Mute Master tone PC_BEEP vol. Phone vol. Mic vol. Line in vol. CD vol. Video vol. Aux vol. PCM out vol. Record Select Record Gain General Purpose 3D Control Power Down Mute Mute Mute Mute Mute Mute Mute Mute Mute POP EAPD
MM5-0 PV3-0 GN4-0 GN4-0 GR4-0 GR4-0 GR4-0 GR4-0 GR4-0 SR2-0 GR3-0 TR2-0 -
0707h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h
-
PR5 PR4 PR3 PR2 PR1 PR0 REV1-0 SPCV
REF ANL DAC ADC 000xh SPDIF SPDIF
28h Extended Audio ID ID1 2Ah Ext Audio Stat/Ctrl 3Ah 62h 64h 66h 68h 7Ch 7Eh DIT Control 1 Vendor Function ZV vol. DIT Control 2 3D Mode Select Vendor ID 1 Vendor ID 2 V *
AMAP LDAC SDAC CDAC -
-
-
xxx4h 0400h
SPSA1-0
SPSR1-0 * "0" "0" "1" "0" *
GL CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY AUD# PRO 2000h * * GL4-0 "0" "0" * "1" "0" * * * * * TX-3 "0" "0" * "0" "0" * TX-7 EXEN GR4-0 TX-8 DMU UDS "1" "0" "1" "0" "0" "1"
3AWE
*
*
0224h x808h 0040h 0C00h 594Dh 4803h
Mute MSEL "0" "0" "1" "1"
ZEN ZAC * "0" "0" * "1" "0"
WM1-0 "1" "1" "0" "0"
"1" "1"
Note) The * bits of 62h and 66h should not be changed from the default value. Do not access to 5Ah and 60h because they are LSI test registers.
00h : Reset (Read/Write reset, Default: 0040h)
D15 "0" D14 "0" D13 "0" D12 "0" D11 "0" D10 "0" D9 "0" D8 "0" D7 "0" D6 "1" D5 "0" D4 "0" D3 "0" D2 "0" D1 "0" D0 "0"
When any value is written to this register, all registers except for the lower 4 bits of 26h:Power Down are reset to the default value.
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02h : Master Volume (Read/Write, Default: 8000h)
D15 Mute D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ML5-0 MR5-0
Mute..............Setting this bit to "1" mutes both left and right channels of the line output. ML5-0...........These bits determine the volume level of the line output left channel by 1.5dB step. The volume range is from 0dB to -46.5dB. When all bits are set to "0", volume is maximum (0dB) and when they are set to "011111b", volume is minimum (-46.5dB). And when ML5 bit is set to "1", the volume level is minimum (-46.5dB), then their status become "011111b". MR5-0...........These bits determine the volume level of the line output right channel by 1.5dB step. Setting to them is the same as the upper ML5-0 bits.
04h : LNLVL Volume (Read/Write, Default: 0000h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -
Though the register can be written any value, it does not function. 0000h is always read out.
06h : Master Volume Mono (Read/Write, Default: 8000h)
D15 Mute D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MM5-0
Mute..............Setting this bit to "1" mutes the monaural output. MM5-0..........These bits determine the volume level of the monaural output by 1.5dB step. The volume range is from 0dB to -46.5dB. When all bits are set to "0", volume is maximum (0dB) and when they are set to "011111b", volume is minimum (-46.5dB). And when MM5 bit is set to "1", the volume level is minimum (-46.5dB), then their status become "011111b"
08h : Master Tone (Read/Write, Default: 0707h)
D15 D14 D13 D12 D11 D10 D9 BA2-0 D8 D7 D6 D5 D4 D3 D2 D1 TR2-0 D0
BA2-0 ...........These bits determine the bass level by 1.5dB step. The tone range is from 0dB to +10.5dB. When all bits are set to "0", tone is maximum (+10.5dB) and when all bits are set to "1", tone is minimum (0dB) TR2-0............These bits determine the treble level by 1.5dB step. Setting to them is the same as the upper BA2-0.
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YMF753
0Ah : PC_BEEP Volume (Read/Write, Default: 0000h)
D15 Mute D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PV3-0
Mute..............Setting this bit to "1" mutes the PC_BEEP. PV3-0............These bits determine the volume level of the PC_BEEP by 3.0dB step. The volume range is from 0dB to -45dB. When all bits are set to "0", volume is maximum (0dB) and when all bits are set to "1", volume is minimum (-45dB).
0Ch : Phone Volume (Read/Write, Default: 8008h)
D15 Mute D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 GN4-0 D1 D0
Mute..............Setting this bit to "1" mutes the Phone. GN4-0 ...........These bits determine the volume level of the Phone by 1.5dB step. The volume range is from +12dB to -34.5dB. When all bits are set to "0", volume is maximum (+12dB) and when all bits are set to "1", volume is minimum (-34.5dB).
0Eh : Mic Volume (Read/Write, Default: 8008h)
D15 Mute D14 D13 D12 D11 D10 D9 D8 D7 D6 20dB D5 D4 D3 D2 GN4-0 D1 D0
Mute..............Setting this bit to "1" mutes the Microphone. 20dB .............Setting this bit to "1" increases +20dB for the microphone volume, which is set to GN4-0 bits. GN4-0 ...........These bits determine the volume level of the microphone by 1.5dB step. The volume range is from +12dB to -34.5dB. When all bits are set to "0", volume is maximum (+12dB) and when all bits are set to "1", volume is minimum (-34.5dB). 10h : Line in Volume (Read/Write, Default: 8808h) 12h : CD Volume (Read/Write, Default: 8808h) 14h : Video Volume (Read/Write, Default: 8808h) 16h : Aux Volume (Read/Write, Default: 8808h) 18h : PCM out Volume (Read/Write, Default: 8808h)
D15 Mute D14 D13 D12 D11 D10 GL4-0 D9 D8 D7 D6 D5 D4 D3 D2 GR4-0 D1 D0
Mute..............Setting this bit to "1" mutes both left and right channels of the each source. GL4-0 ...........These bits determine the volume level of the left channel by 1.5dB step. The volume range is from +12dB to -34.5dB. When all bits are set to "0", volume is maximum (+12dB) and when all bits are set to "1", volume is minimum (-34.5dB). GR4-0 ...........These bits determine the volume level of the right channel by 1.5dB step. Setting to them is the same as the upper GL4-0 bits.
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YMF753
1Ah : Record Select (Read/Write, Default: 0000h)
D15 D14 D13 D12 D11 D10 D9 SL2-0 D8 D7 D6 D5 D4 D3 D2 D1 SR2-0 D0
SL2-0 ............These bits select the left channel source for A/D converter. SR2-0............These bits select the right channel source for A/D converter.
SL2 0 0 0 0 1 1 1 1 SL1 0 0 1 1 0 0 1 1 SL0 0 1 0 1 0 1 0 1 Left Source Mic CD L-ch Video L-ch Aux L-ch Line in L-ch Stereo Mix L-ch Mono Mix Phone SR2 0 0 0 0 1 1 1 1 SR1 0 0 1 1 0 0 1 1 SR0 0 1 0 1 0 1 0 1 Right Source Mic CD R-ch Video R-ch Aux R-ch Line in R-ch Stereo Mix R-ch Mono Mix Phone
1Ch : Record Gain (Read/Write, Default: 8000h)
D15 Mute D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GL3-0 GR3-0
Mute..............Setting this bit to "1" mutes the source which is selected at 1Ah:Record Select. GL3-0 ...........These bits determine the volume level, which is selected at 1Ah:Record Select SL2-0 bits, by 1.5dB step. The volume range is from 0dB to +22.5dB. When all bits are set to "0", volume is minimum (0dB) and when all bits are set to "1", volume is maximum (+22.5dB). GR3-0 ...........These bits determine the volume level, which is selected at 1Ah:Record Select SR2-0 bits, by 1.5dB step. Setting to them is the same as the upper GL3-0 bits.
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YMF753
20h : General Purpose (Read/Write, Default: 0000h)
D15 POP D14 D13 3D D12 D11 D10 D9 MIX D8 MS D7 LPBK D6 D5 D4 D3 D2 D1 D0 -
POP...............This bit selects whether PCM (DAC) output is gone through the 3D and Tone (Bass / Treble) or not. "0" : PCM (DAC) output is gone through the 3D and Tone. "1" : PCM (DAC) output is bypassed the 3D and Tone. 3D .................This bit selects whether 3D enhancement is used or not. "0" : Off "1" : On MIX ..............This bit selects the output to MONO_OUT(No.37). "0" : All mixing sources are output to MONO_OUT. "1" : The microphone input is output to MONO_OUT. MS ................This bit selects either MIC1 or MIC2 for the microphone input. "0" : MIC1 (No.21) "1" : MIC2 (No.22) LPBK............This bit selects data to the D/A converter. "0" : Data from the AC-Link "1" : Loopback from A/D converted data
22h : 3D Control (Read/Write, Default: 0000h)
D15 D14 D13 D12 D11 D10 WD3-1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -
WD3-1 ..........These bits determine the wide level of 3D enhancement (wide stereo). The wide range is from 0% to 100%. When all bits are set to "0", wide level is 0% and when all bits are set to "1", wide level is 100%.
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YMF753
26h : Power Down (Read/Write, Default: 000xh)
D15 EAPD D14 D13 PR5 D12 PR4 D11 PR3 D10 PR2 D9 PR1 D8 PR0 D7 D6 D5 D4 D3 REF D2 ANL D1 DAC D0 ADC
EAPD............This bit controls the state of EAPD (No.47) pin. "0" : Low "1" : High PR5 ...............This bit controls the power state of the clock oscillation circuit. "0" : Normal "1" : Power down PR4 ...............This bit controls the power state of the AC-Link. "0" : Normal "1" : Power down PR3 ...............This bit controls the power state of the analog mixer. "0" : Normal "1" : Power down (Vref off) PR2 ...............This bit controls the power state of the analog mixer. "0" : Normal "1" : Power down (Vref still on) PR1 ...............This bit controls the power state of the D/A converter. "0" : Normal "1" : Power down PR0 ...............This bit controls the power state of the A/D converter. "0" : Normal "1" : Power down REF...............This bit is Read Only, and indicates the state of Vref. "0" : Ground level "1" : Reference voltage ANL..............This bit is Read Only, and indicates the state of the analog mixer. "0" : The analog mixer does not work. "1" : The analog mixer works normally. DAC..............This bit is Read Only, and indicates the state of the D/A converter. "0" : The D/A converter does not work. "1" : The D/A converter works normally. ADC..............This bit is Read Only, and indicates the state of the A/D converter. "0" : The A/D converter does not work. "1" : The A/D converter works normally. Note) When YMF753 is the Secondary CODEC, and both PR5 and PR4 are set to "1", these bits are not cleared by Warm Reset.
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YMF753
28h : Extended Audio ID (Read Only, Default: xxx4h)
D15 ID1 D14 ID0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
SPDIF
D1 -
D0 -
REV1-0
AMAP LDAC SDAC CDAC
ID1,ID0.........These bits indicate CODEC ID. The states are determined by setting both No.46 and 45 pins. When MSEL is high, they are fixed to "Primary ID00".
ID1# (No.46) Pin Status OPEN ("H") OPEN ("H") GND ("L") GND ("L") Logic Value "0" "0" "1" "1" ID0# (No.45) Pin Status OPEN ("H") GND ("L") OPEN ("H") GND ("L") Logic Value "0" "1" "0" "1" CODEC ID Configuration Primary ID00 Secondary ID01 Secondary ID10 Secondary ID11
REV1-0.........These bits are hardwired to "01b", which indicates AC'97 Revision 2.2 Compliant. AMAP...........This bit is hardwired to "1". It indicates that the PCM DAC uses data of the standard slot into twelve slots, as the following table.
CODEC ID 00 01 10 11 Slot Number PCM Left DAC Slot 3 Slot 3 Slot 7 Slot 6 PCM Right DAC Slot 4 Slot 4 Slot 8 Slot 9 Original definition (master) Original definition (docking) Left / Right surround channels Center / LFE channels
LDAC ...........When PCM DAC uses the LFE channel, this bit is set to "1". SDAC ...........When PCM DAC uses the surround channels, this bit is set to "1". CDAC ...........When PCM DAC uses the center channel, this bit is set to "1". SPDIF ...........This bit is hardwired to "1", which indicates that SPDIF output is compliant with AC'97 Revision 2.2.
2Ah : Ext Audio Stat/Ctrl (Read/Write, Default: 0400h)
D15 D14 D13 D12 D11 D10 SPCV D9 D8 D7 D6 D5 D4 D3 D2
SPDIF
D1 -
D0 -
SPSA1-0
SPCV ............This bit is hardwired to "1", which indicates that SPDIF output configuration is valid. SPSA1-0 .......These bits select DIT output slot.
SPSA1 0 0 1 1 SPSA0 0 1 0 1 L-ch Slot Number Slot 3 Slot 7 Slot 6 Slot 10 R-ch Slot Number Slot 4 Slot 8 Slot 9 Slot 11
SPDIF ...........This bit selects whether the SPDIF signal is output from DIT or not. "0" : DIT is power down state, and outputs low level. "1" : SPDIF signal is output from DIT.
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YMF753
3Ah : DIT Control 1 (Read/Write, Default: 2000h)
D15 V D14 D13 D12 D11 GL D10 CC6 D9 CC5 D8 CC4 D7 CC3 D6 CC2 D5 CC1 D4 CC0 D3 D2 D1 D0 SPSR1-0 PRE COPY AUD# PRO
V ...................This bit determines V-bit (Validity flag) output from DIT. "0" : The Validity flag is "0" (Valid). "1" : The Validity flag is "1" (Invalid). SPSR1-0 .......These bits determine sampling frequency of channel status output from DIT. These bits are hardwired to "10b", because SPDIF output of YMF753 is fixed to 48kHz. GL.................This bit determines bit15: L-bit (Generation status) of channel status output from DIT. The sense of Generation status is different by Category Code. CC6-0 ...........These bits determine bit14-8: Category Code of channel status output from DIT. PRE...............This bit determines bit3: Pre-emphasis of channel status output from DIT. "0" : without Pre-emphasis "1" : with Pre-emphasis of 50/15s COPY ...........This bit determines bit2: Copy protection of channel status output from DIT. "0" : Copyright "1" : No Copyright AUD# ...........This bit determines bit1 of channel status output from DIT. If AC-3 or DTS is output, set to "1". "0" : PCM format "1" : Non-PCM format PRO ..............This bit determines bit0 of channel status output from DIT. It should be set to "0" as Consumer use.
62h : Vendor Function (Read/Write, Default: 0224h)
D15 * D14 * D13 * D12 * D11 * D10 * D9
*
D8 *
D7 *
D6 *
D5 *
D4 *
D3
D2
D1 *
D0 *
TX-7 EXEN
TX-7 .............This bit selects the pin function of No.47. "0" : EAPD "1" : DIT EXEN ...........This bit selects whether EXT24M pin outputs clock or not. "0" : EXT24M is power down state, and outputs low level. "1" : EXT24M outputs the clock. The bits except TX-7 and EXEN should not be changed from the default value.
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YMF753
64h : ZV Port Volume (Read/Write, Default: 8808h or C808h)
D15 D14 D13 D12 D11 D10 GL4-0 D9 D8 D7 ZEN D6 ZAC D5 D4 D3 D2 GR4-0 D1 D0 Mute MSEL
Mute..............Setting this bit to "1" mutes both left and right channels of the ZV port. MSEL ...........This bit is read only, and indicates the status of No.40 MSEL pin. "0" : Low "1" : High GL4-0 ...........These bits determine the volume level of the ZV port left channel by 1.5dB step. The volume range is from +12dB to -34.5dB. When all bits are set to "0", volume is maximum (+12dB) and when all bits are set to "1", volume is minimum (-34.5dB). ZEN ..............This bit selects whether ZV port is used or not. "0" : ZV port is power down state, and can not be used. "1" : ZV port can be used. ZAC ..............This bit is read only, and indicates whether the bit clock (ZV_BCK) is input to ZV port or not. "0" : The bit clock (ZV_BCK) is not input. "1" : ZV port is active because the bit clock (ZV_BCK) is input. GR4-0 ...........These bits determine the volume level of the ZV port right channel by 1.5dB step. Setting to them is the same as the upper GL4-0 bits.
66h : DIT Control 2 (Read/Write, Default: 0040h)
D15 D14 D13 D12 D11 D10 D9 D8 * D7 * D6 * D5 TX-3 D4 * D3 D2 D1 D0 TX-8 DMU UDS 3AWE
TX-3 .............SPDIF signal is output from No.43 DIT, if this bit is set to "1" at MSEL= "Low". TX-8 .............SPDIF signal is output from No.48 DIT, if this bit is set to "1" at MSEL= "Low". DMU.............Setting this bit to "1" mutes audio data output from DIT. UDS ..............This bit selects the data output from DIT. "0" : Data from the AC-Link "1" : Data from A/D converter 3AWE ...........This bit selects whether 3Ah register can be written or not. "0" : 3Ah register is Read Only. "1" : 3Ah register is Read / Write. D8, D7, D6 and D4 should not be changed from the default value.
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YMF753
68h : 3D Mode Select (Read/Write, Default: 0C00h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 WM1-0
WM1-0 .........These bits select the mode of 3D / Bass / Treble according to the frequency response of the speaker.
WM1 0 0 1 1 WM0 0 1 0 1 3D Mode Do not select. DeskTop Notebook PC 1 Notebook PC 2 Target Speaker - Standard Speaker Small Speaker Smaller Speaker Speaker Size - 5 - 12 cm 3 cm 1.5 cm
7Ch : Vendor ID 1 (Read Only, Default: 594Dh)
D15 "0" D14 "1" D13 "0" D12 "1" D11 "1" D10 "0" D9 "0" D8 "1" D7 "0" D6 "1" D5 "0" D4 "0" D3 "1" D2 "1" D1 "0" D0 "1"
7Eh : Vendor ID 2 (Read Only, Default: 4803h)
D15 "0" D14 "1" D13 "0" D12 "0" D11 "1" D10 "0" D9 "0" D8 "0" D7 "0" D6 "0" D5 "0" D4 "0" D3 "0" D2 "0" D1 "1" D0 "1"
7Ch and upper 8 bits of 7Eh indicate Yamaha vendor ID, which is "YMH". "Y" is 59h, "M" is 4Dh, and "H" is 48h with ASCII code. Lower 8 bits of 7Eh is YMF753 revision ID (03h).
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March 6, 2001
YMF753
SYSTEM CONNECTION DIAGRAM
Mono Out L-ch LNLVL Out R-ch LNLVL Out L-ch LINE Out R-ch LINE Out
PC Beep Phone L-ch AUX R-ch AUX L-ch Video R-ch Video L-ch CD CD Ground R-ch CD MIC L-ch Line IN R-ch Line IN
PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 LINE_IN_L LINE_IN_R MIC2
CAP1 MONO_OUT LNLVL_OUT_L LNLVL_OUT_R LINE_OUT_L LINE_OUT_R
CAP6 CAP5 CAP4 CAP3 CAP2
Vref Vrefout MSEL AVdd1,2 AVss1,2
+5.0V
YMF753-S
DVdd1,2 DVss1,2 +3.3V
SDATA_IN SDATA_OUT BIT_CLK SYNC RESET# EXT24M EAPD (DIT) ZV_LR ZV_SIN ZV_BCK
XTL_OUT XTL_IN
SDATA IN SDATA OUT BIT CLK SYNC RESET#
ZV BCK ZV SIN ZV LR EAPD / DIT DGND AGND
1)
Power and Ground To get the most out of analog performance, it is necessary to split the ground into analog and digital blocks. Analog ground and digital ground earth at one point closed to the initial ground supply of the board. The layout of the ground pattern should be designed as large as possible and the impudence should be reduced to prevent from receiving ambient noise. In addition, use 0.1F and 47F capacitors to connect between the analog voltage pin and the analog ground as well as between the digital supply pin and the digital ground.
2)
Reference Voltage As the reference voltage determines all analog signals' reference levels of YMF753, noise generated from the reference voltage could affect the YMF753's analog performance. To stabilize the YMF753's reference voltage, insert a 0.1F ceramic capacitor in parallel with a 22F capacitor between Vref pin and the ground. The 0.1F ceramic capacitor should be designed as close to the Vref pin as possible
3)
Master Clock To suppress the master clock from affecting its surroundings, it is recommended to keep the master clock guarded on the ground so the noise can be reduced.
4)
Unused Analog Input / Output pins For the unused analog input pins, short them through a 0.1F ceramic capacitor to the analog ground. For the unused analog output pins, they should be left opened.
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YMF753
5) Recommended Analog Voltage Circuit YMF753 is presumed that it is made to work in the analog power supply formed from +5.00.25V power supply, because the range of analog operating voltage is being made +4.0V to +5.25V. The recommended circuit to form the analog power supply from +5V power supply is shown in below.
+5.0V
470 W
100 F
0.1 F 0.1 F
+4.3V
To YMF753's AVdd1,2
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March 6, 2001
YMF753
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Analog Supply Voltage Digital Supply Voltage Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Note) DVSS = AVSS = 0V Symbol AVDD DVDD VINA VIND TOP TSTG Min. -0.3 -0.5 -0.5 -0.5 0 -50 Max. 7.0 7.0 AVDD + 0.5 DVDD + 0.5 70 125 Unit V V V V C C
2. Recommended Operating Conditions
Parameter Analog Operating Voltage Digital Operating Voltage Operating Ambient Temperature Note) DVSS = AVSS = 0V When using a recommended analog voltage circuit, the output serves as AVDD (typical 4.3V). Symbol AVDD DVDD TOP Min. 4.00 4.75 3.135 0 Typ. 5.00 5.00 3.30 25 Max. 5.25 5.25 3.465 70 Unit V V V C
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YMF753
3. DC Characteristics
3-1. AC-Link Parameter Input Voltage Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Low Level Input Leakage Current Output Leakage Current Symbol VIN VIH VIL VOH VOL Hi-Z IOH = -5mA IOL = 5mA Condition Min. -0.30 0.65 DVDD 0.9 DVDD -10 -10 Typ. Max. DVDD + 0.30 0.35 DVDD 0.1 DVDD 10 10 Unit V V V V V A A
Note) Applicable to RESET#, SYNC, BIT_CLK, SDATA_IN and SDATA_OUT. 3-2. Miscellaneous Parameter Input Voltage High Level 1 Input Voltage Low Level 1 Input Voltage High Level 2 Input Voltage Low Level 2 Input Voltage High Level 3 Input Voltage Low Level 3 Output Voltage High Level 1 Output Voltage Low Level 1 Output Voltage High Level 2 Output Voltage Low Level 2 Output Voltage High Level 3 Output Voltage Low Level 3 Pull-up Resistor Pull-down Resistor *2 : Applicable to MSEL. *3 : Applicable to ZV_LR, ZV_SIN and ZV_BCK. *4 : Applicable to EAPD. *5 : Applicable to DIT(No.43). *6 : Applicable to EXT24M and DIT(No.48). Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 RONUP *1 *1 *2 *2 *3, DVDD=3.3V *3, DVDD=5.0V *3, DVDD=3.3V *3, DVDD=5.0V *4, IOH = -4mA *4, IOL = 4mA *5, IOH = -2mA *5, IOL = 2mA *6, IOH = -2mA *6, IOL = 2mA ID0#, ID1# Condition Min. 0.7 DVDD 0.8 AVDD 2.0 0.7 DVDD 0.65 AVDD 0.65 AVDD DVDD - 0.4 Typ. 100 100 Max. 0.3 DVDD 0.2 AVDD 0.8 0.3 DVDD 0.4 0.4 0.4 Unit V V V V V V V V V V V V V V kW kW
RONDW *3
Note) *1 : Applicable to XTL_IN, ID0# and ID1#.
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YMF753
4. AC Characteristics (Under recommended operating conditions, Capacitor load=50pF)
4-1. Reset Parameter Cold Reset (SDATA_OUT="L", SYNC="L") RESET# active low pulse width RESET# inactive to BIT_CLK start up delay Warm Reset SYNC active high pulse width SYNC inactive to BIT_CLK start up delay Tsync_high Tsync2clk 1.0 162.8 s ns Trst_low Trst2clk 1.0 162.8 s ns Symbol Min. Typ. Max. Unit
Cold Reset
Trst2clk
Trst_low
RESET#
VIL
BIT_CLK
Warm Reset
Tsync2clk Tsync_high
SYNC
VIH
BIT_CLK
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YMF753
4-2. AC-link Interface Parameter BIT_CLK frequency BIT_CLK clock period BIT_CLK output jitter BIT_CLK low pulse width BIT_CLK high pulse width SYNC frequency SYNC period SYNC low pulse width SYNC high pulse width SDATA_OUT, SYNC setup time SDATA_OUT hold time SDATA_IN delay time AC-link Low Power Mode End of slot 2 to BIT_CLK, SDATA_IN low BIT_CLK
Tclk_high Tclk_low
Symbol
Min. -
Typ. 12.288 81.4 40.7 40.7 48.0 20.8 19.5 1.3 -
Max. 750 45.0 45.0 15.0 1.0
Unit MHz ns ps ns ns kHz s s s ns ns ns s
Tclk_period Tclk_low Tclk_high Tsync_period Tsync_low Tsync_high Tsetup Thold Tco Ts2_pdown
36.0 36.0 10.0 20.0 -
BIT_CLK
Tclk_period
SYNC
Tsync_high Tsync_low
SYNC
Tsync_period
Data Output and Input Timing
Tco Tsetup
BIT_CLK SDATA_IN
Thold
SDATA_OUT, SYNC
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March 6, 2001
YMF753
AC-link Low Power Mode
Slot1 Slot2
BIT_CLK SDATA_OUT
Write to 26h
Data PR4
Don't Care Ts2_pdown
SDATA_IN
4-3. Master Clock & External Clock Out Parameter XTL_IN, EXT24M clock period XTL_IN clock duty EXT24M clock duty XTL_IN & EXT24M Symbol Tcycle Duty-xtl Duty-ext Min. 40 40 Typ. 40.69 Max. 60 60 Unit ns % %
XTL_IN EXT24M
Tcycle
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March 6, 2001
YMF753
4-4. Zoomed Video Port Parameter ZV_BCK frequency ZV_BCK duty ZV_LR delay time ZV_LR setup time ZV_SIN setup time ZV_SIN hold time Zoomed Video Port
1/fBCK
Symbol fBCK DBCK tLRD tLRS tDS tDH
Min. 32fs 40 120 32 32 2
Typ. 48fs 50 -
Max. 64fs 60 -
Unit kHz % ns ns ns ns
ZV_BCK
tDS tDH
ZV_SIN
tLRD tLRS
ZV_LR
5. Power Consumption
Parameter Normal Operating AVDD = 4.3V / DVDD = 3.3V AVDD = 5.0V / DVDD = 5.0V AVDD = 4.3V AVDD = 5.0V DVDD = 3.3V DVDD = 5.0V Power Down Mode (PR0-PR5=0) AVDD = 4.3V / DVDD = 3.3V AVDD = 5.0V / DVDD = 5.0V AVDD = 4.3V AVDD = 5.0V DVDD = 3.3V DVDD = 5.0V 7 12 2 4 10 20 A A A A A A 35 43 8 12 45 55 mA mA mA mA mA mA Min. Typ. Max. Unit
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March 6, 2001
YMF753
6. Analog Characteristics
Parameter Full Scale Line Input Full Scale Microphone Input (0dB) Full Scale Microphone Input (+20dB) Full Scale Line Output Analog S/N CD to LINE_OUT Stereo input except CD to LINE_OUT Analog Frequency Response S/N : D/A converter (fs=48kHz) S/N : A/D converter (fs=48kHz) THD+N : Line Output AVDD=5.0V AVDD=4.3V D/A & A/D Frequency Response Transition Band Stop Band Stop Band Rejection Out-of-Band Rejection Group Delay Power Supply Rejection Rate (1kHz) Crosstalk between Inputs Channels Attenuation & Gain Step PC_BEEP Other than PC_BEEP Input Impedance Input Capacitor Vrefout Voltage 10 7.5 AVDD / 2 3.0 1.5 dB dB kW pF V 40 -70 20 19,200 28,800 70 40 1 90 20 85 75 90 85 -70 -68 -65 -62 19,200 28,800 90 95 20,000 dB dB Hz dB dB dB dB Hz Hz Hz dB dB ms dB dB Min. Typ. AVDD / 5 AVDD / 5 AVDD / 50 AVDD / 5 Max. Unit Vrms Vrms Vrms Vrms
Note) Typical conditions : TOP=25C, DVDD=3.3V, AVDD=4.3V to 5.0V, 1kHz input sine wave, fs=48kHz, 0dB=AVDD/5 Vrms, 10kW / 50pF S/N (dynamic range) measurement: -60dB input, THD+N measurement: -3dB input
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YMF753
EXTERNAL DIMENSIONS
9.000.40 7.000.30
36 25
C-PK48SP-2
37
24
7.000.30
48 13 1 12
0.20TYP or 0.18TYP
1.40TYP or 1.45TYP
P-0.50TYP
0 MIN. (STAND OFF)
1.85MAX. (Installation height)
(1.0)
0-10
LEAD THICKNESS : 0.125TYP or 0.17TYP
0.500.20
The shape of the molded corner may slightly different from the shape in this diagram. The figures in the parenthesis ( ) should be used as a reference. Plastic body dimension do not include burr of resin. UNIT : mm Note : The LSIs for surface mounting need for special care on storage and soldering conditions. For detailed information, please contact your nearest agent of Yamaha.
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9.000.40
March 6, 2001
YMF753
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL, OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANY THIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRANGIMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE.
Note) The specifications of this product are subject to improvement change without prior notice.
AGENCY
YAMAHA CORPORATION
Address inquires to : Semi-conductor Sales & Marketing Department
- Head Office 203, MatsunokiJima, Toyooka-mura. Iwata-gun, Shizuoka-ken, 438-0192 Tel. +81-539-62-4918 Fax. +81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. +81-6-6633-3690 Fax. +81-6-6633-3691
- Tokyo Office - Osaka Office
26 All rights reserved (c) 2001 YAMAHA CORPORATION
March in Japan Printed 6, 2001

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